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  publication# 080146 rev: h amendment: / 0 issue date: october 1999 am7920 subscriber line interface circuit the am7920 subscriber line interface circuit implements the basic telephone line interface functions, and enables the design of low cost, high performance, pots line interface cards. distinctive characteristics  control states: active, ringing, standby, and disconnect  low standby power (35 mw)  ?19 v to ?58 v battery operation  on-hook transmission  two-wire impedance set by single external impedance  programmable constant-current feed  programmable loop-detect threshold  programmable ring-trip detect threshold  no ?5 v supply required  current gain = 500  on-chip thermal management (tmg) feature  four on-chip relay drivers and relay snubbers, 1 ringing and 3 general purpose (32 plcc) block diagram controller c2 c1 rsn two-wire interface hpa hpb signal transmission input decoder and control off-hook detector ring-trip detector power-feed da db bgnd vcc vbref rdc agnd/dgnd vtx vbat a(tip) b(ring) ringout det cas ryout1 rd tmg d1 relay driver ring relay driver relay driver relay driver d2 d3 ryout2 ryout3
2 am7920 data sheet ordering information standard products legerity standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. am7920 s c temperature range c = commercial (0c to +70c)* package type j = 32-pin plastic leaded chip carrier (pl 032) device number/description am7920 subscriber line interface circuit ?1 performance grade ?1 53 db longitudinal balance ?2 63 db longitudinal balance valid combinations list configurations planned to be supported in volume for this device. consult the local legerity sales office to confirm availabil- ity of specific valid combinations, to check on newly released combinations, and to obtain addi- tional data on legerity?s standard military?grade products. valid combinations note: * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ?40c to +85c is guaranteed by characterization and periodic sampling of production units. valid combinations am7920 ?1 ?2 jc sc s = 28-pin small outline integrated circuit (sow 028)
slic products 3 connection diagrams top view da ryout2 ryout3 tmg vbat d2 d1 nc nc det rd hpb hpa vtx vbref rsn agnd nc ryout1 bgnd vcc b(ring) a(tip) db ringout c2 nc rdc 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 4 3 2 1 32 31 30 cas d3 nc c1 notes: 1. pin 1 is marked for orientation. 2. nc = no connect bgnd vcc ringout ryout1 ryout2 tmg vbat d2 d1 det nc b(ring) a(tip) db da rd hpb rsn hpa vbref vtx agnd/dgnd 1 2 3 4 5 6 7 8 9 10 11 28 27 26 25 24 23 22 21 20 19 18 17 16 15 12 13 14 rdc nc cas nc c2 c1 28-pin soic
4 am7920 data sheet pin descriptions pin name type description agnd/dgnd ground analog and digital ground. a(tip) output output of a(tip) power amplifier. bgnd ground battery (power) ground. b(ring) output output of b(ring) power amplifier. c2 ? c1 inputs decoder. ttl compatible. c2 is msb and c1 is lsb. cas capacitor anti-saturation pin for capacitor to filter reference voltage when operating in anti- saturation region. d3 ? d1 input relay driver control. d3 ? d1 control the relay drivers ryout1, ryout2, and ryout3. logic low on d1 activates the ryout1 relay driver. logic low on d2 activates the ryout2 relay driver. logic low on d3 activates the ryout3 relay driver. ttl compatible. da input ring-trip negative. negative input to ring-trip comparator. db input ring-trip positive. positive input to ring-trip comparator. det output switchhook detector. logic low indicates that selected detector is tripped. logic inputs c2 ? c1, e1, and e0 select the detector. open-collector with a built-in 15 k ? pull-up resistor. hpa capacitor high-pass filter capacitor. a(tip) side of high-pass filter capacitor. hpb capacitor high-pass filter capacitor. b(ring) side of high-pass filter capacitor. nc ? no connect. pin not internally connected. rd resistor detect resistor. detector threshold set and filter pin. rdc resistor dc feed resistor. connection point for the dc feed current programming network. the other end of the network connects to the receiver summing node (rsn). ringout output ring relay driver. open-collector driver with emitter internally connected to bgnd. rsn input receive summing node. the metallic current (both ac and dc) between a(tip) and b(ring) is equal to 500 times the current into this pin. the networks that program receive gain, two-wire impedance, and feed resistance all connect to this node. ryout1 output relay/switch driver. open-collector driver with emitter internally connected to bgnd. ryout2 output relay/switch driver. open-collector driver with emitter internally connected to bgnd (plcc only). ryout3 output relay/switch driver. open-collector driver with emitter internally connected to bgnd (plcc only). tmg ? thermal management. external resistor connects between this pin and vbat to offload power from slic. vbat battery battery supply and connection to substrate. vbref ? this is an legerity reserved pin and must always be connected to the vbat pin. vcc power +5 v power supply. vtx output transmit audio. this output is a 0.50 gain version of the a(tip) and b(ring) metallic voltage. vtx also sources the two-wire input impedance programming network.
slic products 5 absolute maximum ratings storage temperature ......................... ? 55 c to +150 c v cc with respect to agnd/dgnd ..... ? 0.4 v to +7.0 v v bat with respect to agnd/dgnd: continuous..................................... +0.4 v to ? 70 v 10 ms ............................................. +0.4 v to ? 75 v bgnd with respect to agnd/dgnd........ +3 v to ? 3 v a(tip) or b(ring) to bgnd: continuous ......................................... v bat to +1 v 10 ms (f = 0.1 hz) ............................. ? 70 v to +5 v 1 s (f = 0.1 hz) ................................ ? 80 v to +8 v 250 ns (f = 0.1 hz) .......................... ? 90 v to +12 v current from a(tip) or b(ring).....................150 ma ringout/ryout1,2,3 current.........................50 ma ringout/ryout1,2,3 voltage ........... bgnd to +7 v ringout/ryout1,2,3 transient ....... bgnd to +10 v da and db inputs voltage on ring-trip inputs ..................... v bat to 0 v current into ring-trip inputs .........................10 ma c2 ? c1 and d3 ? d1 input voltage ......................... ? 0.4 v to v cc + 0.4 v maximum power dissipation, continuous, t a = 70 c, no heat sink (see note) in 32-pin plcc package................................1.7 w thermal data: ................................................................ ja in 32-pin plcc package....................... 43 c/w typ esd immunity/pin (hbm) ..................................1500 v note: thermal limiting circuitry on-chip will shut down the cir- cuit at a junction temperature of about 165 c. the device should never see this temperature and operation above 145 c junction temperature may degrade device reliability. see the slic packaging considerations for more information. stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature .............................0 c to +70 c* v cc .....................................................4.75 v to 5.25 v v bat ...................................................... ? 19 v to ? 58 v agnd/dgnd .......................................................... 0 v bgnd with respect to agnd/dgnd ....................... ? 100 mv to +100 mv load resistance on vtx to ground .............. 20 k ? min the operating ranges define those limits between which the functionality of the device is guaranteed. * functionality of the device from 0 c to +70 c is guaranteed by production testing. performance from ? 40 c to +85 c is guaranteed by characterization and periodic sampling of production units.
6 am7920 data sheet electrical characteristics note: * performance grade description test conditions (see note 1) min typ max unit note transmission performance 2-wire return loss 200 hz to 3.4 khz 26 db 1, 4 analog output (vtx) impedance 3 20 ? 4 analog (vtx) output offset voltage ? 50 +50 mv overload level, 2-wire and 4-wire active state 2.5 vpk 2a overload level on hook, r lac = 600 ? 0.77 vrms 2b thd, total harmonic distortion 0 dbm +7 dbm ? 64 ? 55 ? 50 ? 40 db 5 thd, on hook 0 dbm, r lac = 600 ? ? 36 longitudinal capability (see test circuit d) longitudinal to metallic l-t, l-4 balance 200 hz to 1 khz 0 c to +70 c ? 1* 0 c to +70 c ? 2 ? 40 c to +85 c ? 1 ? 40 c to +85 c ? 2 52 63 50 58 db 4 4 1 khz to 3.4 khz 0 c to +70 c ? 1* 0 c to +70 c ? 2 ? 40 c to +85 c ? 1 ? 40 c to +85 c ? 2 52 58 50 53 4 4 longitudinal signal generation 4-l 200 hz to 3.4 khz 40 longitudinal current per pin (a or b) active state 20 27 35 marms 8 longitudinal impedance at a or b 0 to 100 hz 25 ? /pin idle channel noise c-message weighted noise r l = 600 ? 0 c to +70 c r l = 600 ? ? 40 c to +85 c 7 +10 +12 dbrnc 4 psophometric weighted noise r l = 600 ? 0 c to +70 c r l = 600 ? ? 40 c to +85 c ? 83 ? 80 ? 78 dbmp insertion loss and balance return signal (see test circuits a and b) gain accuracy 4- to 2-wire 0 dbm, 1 khz ? 0.20 0 +0.20 db gain accuracy 2- to 4-wire, 4- to 4-wire 0 dbm, 1 khz ? 6.22 ? 6.02 ? 5.82 gain accuracy, 4- to 2-wire on hook ? 0.35 +0.35 4 gain accuracy, 2- to 4-wire, 4- to 4-wire on hook ? 6.37 ? 6.02 ? 5.67 gain accuracy over frequency 300 to 3.4 khz relative to 1 khz ? 0.15 +0.15 gain tracking +3 dbm to ? 55 dbm relative to 0 dbm ? 0.15 +0.15 gain tracking on hook 0 dbm to ? 37 dbm +3 dbm to 0 dbm ? 0.15 ? 0.35 +0.15 +0.35 group delay 0 dbm, 1 khz 4 s 4, 7
slic products 7 electrical characteristics (continued) description test conditions (see note 1) min typ max unit note line characteristics i l , short loops, active state r ldc = 600 ? 20 23 26 ma i l , long loops, active state r ldc = 1930 ? , bat = ? 42.75 v, t a = 25 c 18 19 i l , accuracy, standby state 0.7i l i l 1.3i l constant-current region 18 30 i l , loop current, disconnect state r l = 0 100 a i l lim active, a and b to ground 85 120 ma vab, open circuit voltage v bat = ? 52 v ? 42.75 ? 44 v power supply rejection ratio (v ripple = 100 mvrms), active normal state v cc 50 hz to 3.4 khz 30 40 db 5 v bat 50 hz to 3.4 khz 28 50 effective internal resistance cas pin to v bat 85 170 255 k ? 4 power dissipation on hook, disconnect state 25 70 mw on hook, standby state 35 100 on hook, active state 125 270 off hook, standby state r l = 600 ? 860 1200 off hook, active state r l = 300 ? , r tmg = 2350 ? 450 800 supply currents, battery = ? 48v i cc , on-hook v cc supply current disconnect state standby state active state, bat = ? 48 v 1.7 2.2 6.3 4.0 4.0 8.5 ma i bat , on-hook v bat supply current disconnect state standby state active state, bat = ? 48 v 0.25 0.55 2.8 1.0 1.5 4.8 rfi rejection rfi rejection 100 khz to 30 mhz, (see figure f) 1.0 mvrms 4 receive summing node (rsn) rsn dc voltage i rsn = 0 ma 0 v 4 rsn impedance 200 hz to 3.4 khz 10 20 ? logic inputs (c2 ? c1 and d3 ? d1) v ih , input high voltage 2.0 v v il , input low voltage 0.8 i ih , input high current ? 75 40 a i il , input low current ? 400 logic output (det ) v ol , output low voltage i out = 0.3 ma, 15 k ? to v cc 0.40 v v oh , output high voltage i out = ? 0.1 ma, 15 k ? to v cc 2.4 ring-trip detector input (da, db) bias current ? 500 ? 50 na offset voltage source resistance = 2 m ? ? 50 0 +50 mv 6 i l bat 3 v ? r l 400 + ------------------------------ - t a 25 c = =
8 am7920 data sheet electrical characteristics (continued) relay driver schematics notes: 1. unless otherwise noted, test conditions are bat = ? 52 v, v cc = +5 v, r l = 600 ? , r dc1 = r dc2 = 27.17 k ? , r tmg = 2350 ? , r d = 35.4 k ? , no fuse resistors, c hp = 0.22 f, c dc = 0.1 f, c cas = 0.33 f, d1 = 1n400x, two-wire ac input impedance is a 600 ? resistance synthesized by the programming network shown below. 2. a. overload level is defined when thd = 1%. b. overload level is defined when thd = 1.5%. 3. balance return signal is the signal generated at v tx by v rx . this specification assumes that the two-wire, ac-load impedance matches the programmed impedance. 4. not tested in production. this parameter is guaranteed by characterization or correlation to other tests. 5. this parameter is tested at 1 khz in production. performance at other frequencies is guaranteed by characterization. 6. tested with 0 ? source impedance. 2 m ? is specified for system design only. 7. group delay can be greatly reduced by using a z t network such as that shown in note 1. the network reduces the group delay to less than 2 s and increases 2wrl. the effect of group delay on linecard performance also may be compensated for by synthesizing complex impedance with the qslac ? or dslac ? device. 8. minimum current level guaranteed not to cause a false loop detect. description test conditions (see note 1) min typ max unit note loop detector on threshold r d = 35.4 k ? 11.5 17.3 ma off threshold r d = 35.4 k ? 9.4 14.1 hysteresis r d = 35.4 k ? 0 4.4 relay driver output (ringout, ryout1, ryout2, ryout3) on voltage i ol = 40 ma +0.3 +0.7 v off leakage v oh = +5 v 100 a zener breakover i z = 100 a 6 7.2 v zener on voltage i z = 30 ma 10 ringout bgnd ryout1, ryout2, ryout3 bgnd r rx = 150 k ? r t1 = 75 k ? vtx rsn v rx r t2 = 75 k ? c t1 = 120 pf
slic products 9 table 1. slic decoding state c2 c1 two-wire status det output 0 00 disconnect ring trip 1 01 ringing ring trip 2 10 active loop detector 3 11 standby loop detector table 2. user-programmable components z t is connected between the vtx and rsn pins. the fuse resistors are r f , and z 2win is the desired 2-wire ac input impedance. when computing z t , the internal current amplifier pole and any external stray capacitance between vtx and rsn must be taken into account. z rx is connected from vrx to rsn. z t is defined above, and g 42l is the desired receive gain. r dc1 , r dc2 , and c dc form the network connected to the r dc pin. r dc1 and r dc2 are approximately equal. i loop is the desired loop current in the constant-current region. r d and c d form the network connected from r d to agnd/ dgnd and i t is the threshold current between on hook and off hook. c cas is the regulator filter capacitor and f c is the desired filter cut-off frequency. standby loop current (resistive region). thermal management equations (normal active and tip open states) r tmg is connected from tmg to vbat and saves power within the slic in active and disconnect state constant-currents only. power dissipated in the tmg resistor, r tmg , during active and disconnect states. power dissipated in the slic while in active and disconnect states. z t 250 z 2win 2 r f ? () = z rx z l g 42l ------------ ? 500 z t z t 250 z l 2 r f + () + --------------------------------------------------- - = r dc1 r dc2 1250 i loop --------------- = + c dc 1.5 ms r dc1 r dc2 + r dc1 r dc2 ? ---------------------------------- ? = rd on 510 i t -------- - rd off 415 i t -------- - c d 0.5 ms r d ---------------- - = , = , = c cas 1 3.4 10 5 f c ? ------------------------------ - = i standby v bat 3v ? 400 ? r l + --------------------------------- - = r tmg v bat 6v ? i loop --------------------------------- - 70 ? ?    p rtmg v bat 6v ? i l ? r l () ? () 2 r tmg 70 ? + () 2 ------------------------------------------------------------------------ r tmg ? = p slic v bat i l p rtmg ? r l i l () 2 0.12 w + ? ? =
10 am7920 data sheet dc feed characteristics 0 i l (ma) vab (volts) 30 60 1 2 3 a. load line (typical) notes: 1. 2. 3. v ab i l r l ' 1250 r dc ----------- - r l 'where r l ' r l 2 r f + = , = = v ab 0.857 v bat 3.3 + () i l r dc 300 ----------- ? = v ab 0.857 v bat 1.2 + () i l r dc 300 ----------- ? = r dc = r dc1 + r dc2 = 54.34 k ? bat = ? 48 v a b i l rsn rdc r dc1 r dc2 c dc slic r l a b b. feed programming feed current programmed by r dc1 and r dc2 figure 1. dc feed characteristics
slic products 11 test circuits r t r rx v ab v l r l 2 i l2-4 = 20 log (v tx / v ab ) a. two- to four-wire insertion loss a(tip) b(ring) agnd vtx rsn slic r l 2 r t v ab a(tip) b(ring) agnd vtx rsn slic r l r rx v rx i l4-2 = 20 log (v ab / v rx ) brs = 20 log (v tx / v rx ) b. four- to two-wire insertion loss and balance return signal r t r rx r l 2 r l 2 v rx s1 c s2 v l v l a(tip) b(ring) agnd vtx rsn slic 1 << r l l-4 long. bal. = 20 log (v tx / v l ) l-t long. bal. = 20 log (v ab / v l ) 4-l long. sig. gen. = 20 log (v l / v rx ) c. longitudinal balance v ab s2 open, s1 closed s2 closed, s1 open c
12 am7920 data sheet test circuits (continued) d. two-wire return loss test circuit r r return loss = ? 20 log (2 v m / v s ) z d : the desired impedance; e.g., the characteristic impedance of the line v m z in v s a(tip) b(ring) agnd vtx r sn slic r t2 r rx c t1 r t1 z d v cc a(tip) b(ring) det e1 6.2 k ? r l = 600 ? 15 pf e. loop-detector switching f. rfi test circuit 50 ? l 1 200 ? 200 ? c 1 c 2 b hf gen vtx a l 2 cax 33 nf cbx 33 nf rf 1 rf 2 50 ? 50 ? 1.5 vrms 80% amplitude modulated 100 khz to 30 mhz slic under test
slic products 13 test circuits (continued) g. am7920 test circuit vcc r d rd vtx agnd/ dgnd rsn r rx r dc2 r dc1 c dc r t rdc c2 c1 +5 v vbat det d 1 bgnd ringout hpb c hp hpa db da a(tip) b(ring) cas c cas bat 2.2 nf 2.2 nf v tx v rx a(tip) b(ring) ryout1 tmg r tmg ryout3 ryout3 d1 d2 d3 c d vbref battery ground analog ground digital ground
14 am7920 data sheet physical dimensions pl032 sow028 .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530 .006 .0125 16-038-so28-2_ac sow28 df87 9-3-97 lv 0.045 min. detail a .014 .024 0.86 0.90 0.14 0.20 detail a .050 bsc 114 .697 .728 .324 .350 15 28 .453 .500 .002 .014 .080 .100 .016 .050 0 8
slic products 15 revision summary revision c to revision d ? minor changes were made to the datasheet style and format to conform to legerity standards. revision d to revision e ? absolute maximum ratings: added esd immunity specification. revision e to revision f ? added the 28-pin soic connection diagram and the sc option to the ordering information. revision f to revision g ? the physical dimension (pl032) was added to the physical dimension section. revision g to revision h ? deleted the plastic dip package and references to it. ? updated the pin description table to correct inconsistencies.
16 am7920 data sheet notes: www.legerity.com
slic products 17 notes: www.legerity.com
legerity provides silicon solutions that enhance the performance, speeds time-to-market, and lowers the system cost of our customers' products. by combining process, design, systems architecture, and a complete set of software and hardware support tools with unparalleled factory and worldwide field applications support, legerity ensures its customers enjoy a smoother design experience. it is this commitment to our customers that places legerity in a class by itself.
the contents of this document are provided in connection with legerity, inc. products. legerity makes no representations or war ranties with re- spect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specificati ons and product descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intelle ctual property rights is granted by this publication. except as set forth in legerity's standard terms and conditions of sale, legerity assumes no li ability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of legerit y's product could create a situation where personal injury, death, or severe property or environmental damage may occur. legerity reserves the right to discontinue or make changes to its products at any time without notice. ? 1999 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, dslac and qslac are trademarks of legerity, inc. other product names used in this publication are for identification purposes only and may be trademarks of their respective com panies.
p.o. box 18200 austin, texas 78760-8200 telephone: (512) 228-5400 fax: (512) 228-5510 north america toll free: (800) 432-4009 to contact the legerity sales office nearest you, or to download or order product literature, visit our website at www.legerity.com. to order literature in north america, call: (800) 572-4859 or email: americalit@legerity.com to order literature in europe or asia, call: 44-0-1179-341607 or email: europe ? eurolit@legerity.com asia ? asialit@legerity.com


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